Vax 613 0S Instruction Manual download pdf (Page 90)

The SFB ASIC maintains a ﬂag to indicate if this address is a source or

destination. The ﬁrst write indicates a source; the second write indicates

a destination. The state bit toggles back and forth between the two:

subsequent write addresses supplied to the frame buffer in copy mode

appear alternatively as source and destination addresses. To ascertain the

state of the toggle bit, software performs a write operation to the Pixel Shift

Data may be written to the copy buffer from either the CPU or the VRAM.

Data from the VRAM is received one quadword per read, shifted, and then

stored in one of the 4 quadword locations.

The CPU, however, can perform only 1 longword write per operation. To write

a quadword to the buffer, software must therefore write two locations, that

is, copybuffer0 and copybuffer1. On the write operation to copybuffer1, the

data goes through the shift register and is loaded into the buffer. If the copy

buffer is written by the CPU, the ﬂag is set so that the next VRAM operation

in copy mode will be a write to the frame buffer.

• Line draw modes: opaque (010) and transparent (110)

Line draw mode requires more setup than the other modes. The BRES1,

BRES2, and BRES3 registers must also be written, in addition to the MODE

and TRANSPARENT bits being speciﬁed.

BRES1 (Bresenham register 1)

This register contains the address increment and error increment for the

case of a negative error value. This error increment is always positive.

Note

Value at initialization: 0

The register’s format and contents are:

00151631

MR−0084−93RAGS

ADDRESS INCREMENT 1 ERROR INCREMENT 1

6–10 CXTurbo Graphics Subsystem: 300/500 Models

1 2 ... 85 86 87 88 89 90 91 92 93 94 95 ... 343 344

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Vax 613 0S Instruction Manual Page 90