Vax 613 0S Instruction Manual download pdf (Page 164)

MR−0184−93RAGS

XX XX CCF

Field Value Description

CCF 101 25 MHz

CCF 000 40 MHz

X Reserved

DMA transactions require programming of the 53C94 and 53CF94-2. Refer to the

NCR 53C94-95-96 Advanced SCSI Controller or NCR 53CF94/96-2 Fast SCSI

Controllerfor its programming. The ASIC must be programmed before the 53C94

or 53CF94-2.

9.6.5 Initiation of DMA Transfers

Two registers must be written before a transfer begins:

• The DMA Address Register (Section 8.2.3)

The DMA address register is written with bits <33:02> of the address. This

address increments as data is transferred and need not be rewritten for

continuous, sequential transfers with even address and even transfer counts.

Transfers from memory to a device, which start with odd byte addresses and

ﬁnish with a disconnect, require that the DMA address be decremented by

two before the transfer is continued.

• The DMA interrupt control register (Section 8.2.4)

The DMA interrupt control register is written at the low order byte of the

DMA interrupt control register; the rest of the longword is ignored. The DMA

control register is written:

07 00

MR−0105−93RAGS

DPXXXXAA

Field Description

D DMA direction, 0 for a read of main memory, 1 for a write

P DMA read data prefetch enable, 1 to prefetch

AA DMA address bits <1:0>

9–18 I/O Programming

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Vax 613 0S Instruction Manual Page 164