10.5 Error Insertion for Testing Purposes
Certain hardware errors listed is Table 38 may be intentionally inserted in order
to verify the checkers. Table 41 lists error codes and the corresponding errors’
insertion technique, where possible.
Table 41 Error Insertion Techniques
01 - 04 None
06 - 07 Bad tag parity can be written to any Bcache tag by storing the tag to
8(address) in tag space.
08 Test modes in the Dual SCSI ASIC can be configured to cause this.
09 - 0A Bad S/G entry parity can be written to any S/G entry.
0B - 0C The S/G valid bit can be set to 0 or 1.
0D Test mode in the Dual SCSI ASIC can be configured to cause this.
0E - 0F Software can cause illegal addresses to be generated.
10 - 11 A TURBOchannel option may be able to be configured to cause these.
13 BIU_CTL<BAD_DP> can be set in the CPU to cause this.
12 This can be set up by means of the above mechanism with some cleverness.
14 - 15 This can be caused by referencing a non-existent option.
16 - 18 None
19 BIU_CTL<BAD_DP> can be set in the CPU to cause this.
1A Bad tag parity can be written to any Bcache tag by storing the tag to
8(address) in tag space.
1B BIU_CTL<BAD_TCP> can be used to cause this.
1C Bad tag parity can be written to any Bcache tag by storing the tag to
8(address) in tag space.
10–14 Hardware Exceptions and Interrupts
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