Vax 613 0S Instruction Manual Page 5
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7.3.3 Communication Port 1 Receive DMA
Pointer—1.A004.0040/1.E004.0040............................ 7–7
7.3.4 Printer Port Transmit DMA Pointer—NA/ 1.E004.0050 ............ 7–8
7.3.5 Printer Port Receive DMA Pointer—NA/1.E004.0060 ............. 7–8
7.3.6 ISDN Transmit DMA Pointer—1.A004.0080/1.E004.0080 . . . ....... 7–8
7.3.7 ISDN Transmit DMA Buffer Pointer—1.A004.0090/1.E004.0090 ..... 7–8
7.3.8 ISDN Receive DMA Pointer—1.A004.00A0/1.E004.00A0 ........... 7–9
7.3.9 ISDN Receive DMA Buffer Pointer—1.A004.00B0/1.E004.00B0 ...... 7–9
7.3.10 Data buffers
3-0—1.A004.00C0-1.A004.00F0/1.E004.00C0-1.E004.00F0 . . . ....... 7–9
7.3.11 System Support Register—1.A004.0100/1.E004.0100 .............. 7–10
7.3.12 System Interrupt Register (SIR)—1.A004.0110/1.E004.0110 . ....... 7–12
7.3.13 System Interrupt Mask Register—1.A004.0120/1.E004.0120 . ....... 7–15
7.3.14 System Address Register—1.A004.0130/1.E004.0130 .............. 7–15
7.3.15 ISDN Data Transmit Register—1.A004.0140/1.E004.0140 . . . ....... 7–16
7.3.16 ISDN Data Receive Register—1.A004.0150/1.E004.0150 ........... 7–16
7.3.17 LANCE I/O Slot Register—1.A004.0160/1.E004.0160 .............. 7–16
7.3.18 SCC-0 DMA Slot Register—1.A004.0180/1.E004.0180 ............. 7–17
7.3.19 SCC-1 DMA Slot Register—1.A004.0190/1.E004.0190 ............. 7–17
7.4 Ethernet Station Address ROM Addresses. . ....................... 7–18
7.5 LANCE Register Addresses .................................... 7–21
7.6 SCC Register Addresses ....................................... 7–21
7.7 RTC Register Addresses....................................... 7–23
7.8 ISDN Register Addresses ...................................... 7–24
7.8.1 ISDN Register Addresses (300 Models) . ....................... 7–24
7.8.2 ISDN Register Addresses (400/500/600/700/800/900 Models) . ....... 7–26
8 TURBOchannel Dual SCSI ASIC
8.1 TURBOchannel Dual SCSI Address Map . . . ....................... 8–2
8.2 Internal Registers . . . ........................................ 8–3
8.2.1 Control Interrupt Register (CIR)—1.8004.0000/1.C004.0000 . ....... 8–4
8.2.2 Interrupt Mask Enable Register
(IMER)—1.8004.0004/1.C004.0004 ............................ 8–7
8.2.3 SCSI[x] DMA Address Register (SDAx)—1.8004.1x00/1.C004.1x00 . . . 8–8
8.2.4 SCSI[x] DMA Interrupt Control Register
(DICx0)—1.8004.1x04/1.C004.1x04............................ 8–9
8.2.5 SCSI[x] DMA Unaligned Data[0]
(DUDx0)—1.8004.1x08/1.C004.1x08 ........................... 8–10
8.2.6 SCSI[x] DMA Unaligned Data[1]
(DUDx1)—1.8004.1x0C/1.C004.1x0C . . . ....................... 8–11
8.3 NCR 53C94 Registers (300/400/500 Models). ....................... 8–12
8.4 NCR 53CF94-2 Registers (600/700/800/900 Models) . . . ............... 8–13
8.5 DMA buffers ............................................... 8–14
9 I/O Programming
9.1 I/O Read and Write Restrictions ................................ 9–2
9.2 DMA ..................................................... 9–3
9.2.1 Physical DMA . . . ........................................ 9–3
9.2.2 Virtual DMA (400/500/600/700/800/900 Models) . . . ............... 9–3
9.3 Interrupt Handling During I/O Operations . ....................... 9–4
9.4 TURBOchannel Usage (System-Specific) . . . ....................... 9–5
9.4.1 DMA Size ............................................... 9–5
v
- DEC 3000 300/400/500/600/700 1
- /800/900AXPModels 1
- SystemProgrammer’sManual 1
- Contents 3
- 8 TURBOchannel Dual SCSI ASIC 5
- 9 I/O Programming 5
- 17 DEC 3000 AXP PALcode 8
- Intended Audience 13
- Document Contents 13
- Associated Documents 14
- Conventions 15
- MLO-012116 19
- MLO-012117 22
- MLO-012118 25
- Memory and I/O Addressing 37
- 2.1 Memory Alignment 38
- 2.2 Memory Address Spaces 38
- 2.3 I/O Address Spaces 39
- Memory and I/O Addressing 2–7 43
- 2–8 Memory and I/O Addressing 44
- 2.5 CPU Registers 45
- MR−0061−93RAGS 46
- 2.6 Bcache Tag Space 48
- TURBOchannel I/O Registers 49
- W1C = Cleared when 1 written 51
- 05 04 03 02 01 0031 52
- MR−0066−93RAGS 52
- MR−0068−93RAGS 55
- /800/900) Models 57
- (Alternate address) 58
- 0 P 0 MAGIC # 60
- Bits Access Init. Description 61
- 26:0 R/WU UNP Failing address 61
- 31:27 R/WU UNP Reserved 61
- MR−0072−93RAGS 62
- (from FADR) 62
- Table 11 IMR—1.C281.FFFC 64
- Table 11, 1.C281.FFFC 64
- MR−0074−93RAGS 65
- 3.3.8 Scatter/Gather Map 67
- Address ASIC Registers 69
- 4.1.1 Operation 70
- 4.1.2 Boot Time 71
- 4.1.3 Improper Configuration 72
- 4.1.4 Disabling Memory 72
- 001520 19 18 163133 32 73
- MR−0075−93RAGS 73
- 05 04 0009 08151631 73
- MR−0076−93RAGS 73
- 05 04 002031 75
- MR−0078−93RAGS 75
- 5.2 Organization 78
- V F X PPN XXXX 79
- V P PPN UNP 79
- 6.1 Comparison of Features 82
- 6.2 CXTurbo Address Map 83
- 6.4 SFB ASIC Functions 87
- 6.4.1 Mode Register 89
- 00151631 90
- MR−0084−93RAGS 90
- 6.4.2 Planemask Register 92
- 6.4.3 Raster Op Register 93
- 6.4.4 PixelMask Register 94
- 6.4.6 PixelShift Register 95
- 6.4.7 Address Register 95
- 6.4.8 DEEP Register 95
- CLEAR_INTERRUPT Registers 96
- 6.4.10 Video Timing Registers 96
- (8 ms / 512) * 97
- 0000 BP SYNCH FP PIXELS 98
- 0000 BP SYNCH FP SLs 98
- 6.5 Bt459 RAMDAC 100
- 1.E200.0004 104
- 7.1 IOCTL Address Map 107
- 7.2 System FEPROM 108
- IOCTL ASIC 114
- /900 Models) 123
- Address Content Value 124
- 1.A008.007C TEST Pattern 7 AA 124
- 7.5 LANCE Register Addresses 125
- 7.6 SCC Register Addresses 125
- Address Register 126
- 7.7 RTC Register Addresses 127
- 7.8 ISDN Register Addresses 128
- (continued on next page) 129
- TURBOchannel Dual SCSI ASIC 133
- 8.2 Internal Registers 135
- INTERRUPT CONTROL 136
- Bit Access Reset Description 139
- 15:0 R/W 0 Interrupt Enable 139
- 31:16 R/W 0 Interrupt Mask 139
- Bit Access Reset Descriptron 140
- 07 0008151624 2331 141
- MR−0100−93RAGS 141
- MR−0102−93RAGS 143
- Read Register Write 145
- I/O Programming 147
- 9–2 I/O Programming 148
- 9.2.1 Physical DMA 149
- 9–4 I/O Programming 150
- 9.4.1 DMA Size 151
- 9.4.2 DMA Arbitration 151
- 9.4.3 I/O Timeout 152
- 9.4.4 I/O Conflicts 153
- 9.5 JUNKIO Subsystem 154
- I/O Programming 9–9 155
- 9–10 I/O Programming 156
- I/O Programming 9–13 159
- 9–14 I/O Programming 160
- 9.6 SCSI Interface 161
- 00010BID 00001PAR XXXXXB00 162
- Config 1 Config 2 Config 3 162
- MR−0184−93RAGS 164
- XX XX CCF 164
- 9.6.6 Aborting Transactions 165
- 15314763 171
- MR−0106−93RAGS 171
- PS[CM] Kernel mode 176
- and further information 176
- 11.1 Processor initialization 185
- 11.1.2 SROM Sequence 186
- 11.1.3 SYSROM Sequence 186
- 11.2 Bcache Initialization 187
- Firmware: Overview 189
- Firmware: Overview 12–3 191
- 12.2 Overview of the Console 192
- 12.4 Overview of PALcode 192
- Firmware: Overview 12–5 193
- DEC 3000 AXP Firmware ROMs 195
- 13.3 System ROM Format 197
- MLO-012121 202
- 14.2 Power-On Output 205
- 14.5 System Firmware Entry 209
- 14.5.3 Halt 212
- 14.5.4 Reentry Control 213
- Configuration 215
- 15.1 Main Configuration Table 216
- 15–4 Configuration 218
- from the beginning of 220
- 16.1 Console Device 225
- 16–2 Console 226
- 16.1.3 Attached Terminals 227
- 16.1.4 Built-In Terminals 227
- 16.2 Console Saved State 228
- 16.3 Console Program 228
- 16.3.2 Console Operation 229
- 16–6 Console 230
- 16.4 Console Commands 231
- 16.4.2 CONTINUE 233
- 16.4.3 DEPOSIT 233
- Console 16–11 235
- Console 16–13 237
- 16.4.4 EXAMINE 238
- Console 16–17 241
- 16.4.5 HALT 242
- 16.4.6 HELP 242
- 16.4.7 INITIALIZE 242
- 16.4.8 LOGIN 243
- 16.4.9 REPEAT 243
- 16.4.10 SET[ENV] 244
- 16–22 Console 246
- 16.4.11 SHOW/PRINTENV 249
- 16–26 Console 250
- Console 16–27 251
- 16.4.12 START 254
- 16.4.13 TEST 254
- 16.4.14 ! (COMMENT) 255
- 16.4.15 Console Security 255
- 16.5 Console Data Structures 256
- Console 16–33 257
- 16–34 Console 258
- Console 16–35 259
- HWRPB + 260
- to TBhint block 260
- to HWRPB + DSRDB 262
- are hexadecimal 262
- Name Value 264
- MR−0152−93RAGS 266
- 63 08 0039 266
- SBZ Proc_cnt SBZ PALtype alph 266
- Console 16–43 267
- 16–44 Console 268
- Component Description 269
- Autolock 270
- 16–48 Console 272
- 16–50 Console 274
- Console 16–51 275
- 16.6.1 The FIXUP Routine 277
- 16.6.2 The DISPATCH Routine 278
- Arguments 280
- Description 280
- Returns: 280
- PROCESS_KEYCODE 288
- RESETENV 292
- RESET_TERM 293
- ID-Name Type Description 295
- Console 16–71 295
- SET_TERM_INTR 296
- DEC 3000 AXP PALcode 301
- 17.3 MACHINE_RESET PALcode 305
- 17.4 Machine Check PALcode 305
- 17.5 INTERRUPT PALcode 306
- TURBOchannel Support 307
- Nonvolatile RAM 309
- MLO-012124 310
- MR−0158−93RAGS 312
- LK401_ID 312
- MR−0159−93RAGS 313
- CONSOLE_ID 313
- 19.5 Temporary Storage (TEMP) 314
- 19.8 NVR Security Flags 315
- 19.9 NVR Default Boot Flags 316
- Nonvolatile RAM 19–9 317
- 19.10 NVR SCSI Information 1 318
- Nonvolatile RAM 19–11 319
- 19–12 Nonvolatile RAM 320
- Dense and Sparse Space 321
- A–2 Dense and Sparse Space 322
- Dense and Sparse Space A–3 323
- A.3 Minimum Granularity 324
- A.6 Mapping I/O Addresses 325
- : Longword PA 327
- 0 1 7 0 0 420005 0 XX 327
- A–8 Dense and Sparse Space 328
- Glossary 329
- Glossary–2 330
- Glossary–3 331
- Glossary–4 332
- Technical Support 341
- Electronic Orders 341
- BUSINESS REPLY MAIL 344
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