2.4 TURBOchannel Interface Bit Decode Map for I/O Addresses
An I/O address takes on three forms in the system:
1
1. Software-generated (by the macroinstruction)
2. CPU chip-logic-generated (to the system module)
3. TURBOchannel-interface generated (on the TURBOchannel)
The following bit decode lists describe physical addresses generated by the CPU.
400/500/600/700/800/900 Models Bit Decode List
• I/O and memory space split
33
0
0
1
32
0
1
X
− Main Memory
− TURBOchannel
− RESERVED
MR−0052−93RAGS
• Bit decode map for TURBOchannel
- Option #0, Model 500/500s/800/800s/900
- Option #1, Model 500/500s/800/800s/900
- Option #2, Model 500/500s/800/800s/900
- Option #3, Model 500/500s (Option #0, Model 400/400s/600/600s/700)
- Option #4, Model 500/500s (Option #1, Model 400/400s/600/600s/700)
- Option #5, Model 500/500s (Option #2, Model 400/400s 600/600s/700)
- SCSI Interface, TC0 Control Registers
- IOCTL ASIC, CXTurbo, Model 500
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
31 29
MLO-012119
• Dense vs. sparse space
28
0
1
MR−0054−93RAGS
− Dense Space
− Sparce Space
• When address <31:29> = 110
25
0
1
MR−0055−93RAGS
26
0
1
− SCSI Interface
− TC0 Control Registers
− SCSI Interface
− TC0 Control Registers
If Bit<28> = 1: If Bit<28> = 0:
• When address <31:29> = 111
25
0
1
MR−0056−93RAGS
26
0
1
− IOCTL ASIC
− CXTurbo, Model 500/500S
− IOCTL ASIC
− CXTurbo, Model 500/500S
If Bit<28> = 1: If Bit<28> = 0:
1
These forms are transparent to code executing on the CPU.
Memory and I/O Addressing 2–7
Comments to this Manuals