Vax 613 0S Instruction Manual Page 96

  • Download
  • Add to my manuals
  • Print
  • Page
    / 344
  • Table of contents
  • BOOKMARKS
  • Rated. / 5. Based on customer reviews
Page view 95
6.4.9 START, BCONT, VIDEO_VALID, ENABLE_INTERRUPT,
CLEAR_INTERRUPT Registers
When written to, these registers change the ASIC:
START causes the address in the ADDRESS register to be used for the next
write operation.
BCONT uses a pre-generated address from the former instruction as start
address for the next instruction.
VIDEO_VALID signals that the TURBOchannel writes to the video registers
have completed and video operations may begin. VIDEO_VALID can also be
turned off to update video registers.
ENABLE_INTERRUPT enables or disables interrupt checking, depending on
the low order bit of the data field.
CLEAR_INTERRUPT, if written to, clears an interrupt once it is posted.
6.4.10 Video Timing Registers
There are two clocks in the SFB ASIC.
The TURBOchannel clock
This clock controls the TURBOchannel interface, the SFB datapath logic, and
the VRAM read/write/read modify write logic.
The video clock
A large part of the video subsystem involves displaying data in the VRAM to
the monitor. This display is controlled by the monitor frequency, which is a
combination of the refresh rate and the resolution.
The RAMDAC receives 4 pixels/read from the VRAM interface. Therefore, the
clock that the video subsystem runs on is 1/4 the frequency of the monitor’s
oscillator. The SFB ASIC uses this clock to count active and blank video
cycles, and provide the synch pulse to the RAMDAC for the correct number of
cycles. These registers are programmable through software, and the values
for different resolution/refresh rates can be found in the manufacturer’s
CXTurbo Design Specification.
At initialization, the BLANK signal is sent to the RAMDAC, since the video
registers do not contain valid data. After values for these counters are written
through the TURBOchannel interface, the VIDEO_VALID register must be
written to start the video logic and serial VRAM output to the RAMDAC.
This VIDEO_VALID register is synchronized to the video clock from the
TURBOchannel clock.
6–16 CXTurbo Graphics Subsystem: 300/500 Models
Page view 95
1 2 ... 91 92 93 94 95 96 97 98 99 100 101 ... 343 344

Comments to this Manuals

No comments