Vax 613 0S Instruction Manual download pdf (Page 154)

9.5 JUNKIO Subsystem

The JUNKIO uses the IOCTL ASIC as the bus interface connecting the

TURBOchannel to a 16-bit general purpose I/O bus. This bus services the

following devices:

• AMD 7990 (LANCE)

• Zilog Z85C30 (SCC)

• Dallas Semiconductor DS1287A Real-Time Clock (RTC)

• AMD 79C30A (ISDN)

• FEPROMs

300 models: 768 KB

400/500/600/700/800/900 models: 256 KB

All I/O accesses to the devices are identical, except accesses to the Local Area

Network Contoller for Ethernet (LANCE). The other devices use a specialized I/O

access for DMA access. The Integrated Services Digital Network (ISDN) has a

dedicated 4-bit bus for its DMAs. The LANCE uses an asynchronous interface,

asserts its own signals, and has unique DMA timing.

The ASIC’s 27 on-chip registers consist mainly of DMA address pointers. In

addition, there are four data registers and a few system-related registers that

handle interrupts, interrupt masking, system support, and chip conﬁguration.

9.5.1 IOCTL ASIC Overview

The I/O controller is the TURBOchannel system interface to a number of I/O

devices. The I/O controller connects the TURBOchannel to a 16-bit wide I/O

bus and supplies various control signals to the devices that share this bus. The

controller can perform only one task at a time, either I/O or DMA, and contains

a number of registers that serve as DMA address pointers and hold data that is

being transferred.

The TURBOchannel accesses the register ﬁle by means of an I/O access. The

same I/O access with a changed adddress is performed to communicate with a

device connected to the I/O bus. An I/O access to a device has at most 16 valid

bits, because the I/O bus is 16 bits wide. However, most devices have 8 data pins,

so only one byte is valid.

DMA transmissions are between one and four longwords in length, depending

on the device. The IOCTL ASIC provides an address pointer for each type of

DMA. The pointer is incremented at the end of each transfer. Various interrupts

are set on pointer-related conditions. The IOCTL ASIC stores the data in the

data registers. The data is read from the registers, divided into 16-bit chunks,

and passed one chunk at a time to the device. Once the transfer completes, the

address pointer is incremented. Interrupt bits are set, if special conditions were

meet during the transfer,

On DMA receives, data is passed from the device to the IOCTL ASIC, which

combines the 16-bit chunks into 32-bit chunks. The IOCTL ASIC writes data to

memory, after which the pointer is incremented.

The SIR and SSR have the following functions in I/O programming:

• SIR

9–8 I/O Programming

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