Vax 613 0S Instruction Manual download pdf (Page 13)

Preface

The DEC 3000 300/400/500/600/700/800/900 AXP Models are a family of high-

performance deskside and desktop workstations that use Digital’s DECchip 21064

RISC-style microprocessor. They comprise a family of systems based on the

Digital Alpha AXP architecture, providing a 64-bit computing environment.

Intended Audience

This manual is intended for design engineers and programmers who write such

system-level software as operating systems and drivers. The manual discusses

the format and behavior of speciﬁc hardware architecture as it pertains to writing

system-level programs.

Document Contents

The DEC 3000 300/400/500/600/700/800/900 AXP Models System

Programmer’s Manual is divided into 19 chapters, one appendix, one glossary,

and one index:

• Chapter 1 describes the system and the variations among models.

• Chapter 2 describes the DEC 3000 AXP systems’ address maps, the methods

of addressing I/O space, and system I/O registers, speciﬁcally: memory

alignment, memory address spaces, I/O address space, the TURBOchannel

interface bit decode map for I/O addresses, and address-processing and

Bcache control CPU registers.

• Chapter 3 discusses I/O interface registers—the 300 models’ I/O control and

status registers and the 400/500/600/700/800/900 models’ TURBOchannel

control and status Registers.

• Chapter 4 discusses the 400/500/600/700/800/900 models’ address ASIC,

which controls access to each memory conﬁguration register and to the victim

address counter register and victim address register for caching.

• Chapter 5 discusses the scatter/gather maps used in 400/500/600/700/800/900

models to support virtual DMA—the location, size, and access modes of

scatter/gather registers, their organization, and the performance of read and

write operations on scatter/gather map entries.

• Chapter 6 discusses the CXTurbo graphics subsystem, and covers these topics:

CXTurbo address map, I/O address map, Frame Buffer Control Register, SFB

ASIC functions, Bt459 RAMDAC, and System FEPROM (400/500/600/700/800

/900 models).

• Chapter 7 discusses the IOCTL ASIC and system registers—the IOCTL

address map, system FEPROM, and IOCTL registers.

• Chapter 8 discusses the TURBOchannel Dual SCSI ASIC—address map,

internal registers, 53C94 registers, and DMA buffers.

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Vax 613 0S Instruction Manual Page 13