Vax 613 0S Instruction Manual download pdf (Page 49)

100

101

TURBOchannel I/O Registers

This chapter covers the following topics:

• I/O interface register map (300 models) (Section 3.1)

• I/O control and status registers (300 models) (Section 3.2)

• TURBOchannel interface registers (400/500/600/700/800/900 models)

(Section 3.3)

Note

In all register diagrams, an X in a bit position indicates that the contents

of the bit are ignored when written.

All addresses are dense space addresses, except where dense and sparse

space do not map to the same register. To generate the sparse space

equivalents of dense space addresses, set bit [28] and shift bits [27:2] left

by one, dropping overﬂow bits.

3.1 I/O Interface Register Map (300 Models)

Table 8 lists I/O interface registers for the 300 models.

Table 8 I/O Interface Registers (300 Models)

Address Register Discussed In

1.8000.0000 TURBOchannel dual SCSI ASIC

(Application-Speciﬁc Integrated

Circuit)

Chapter 8

1.A000.0000 IOCTL ASIC (Application-

Speciﬁc Integrated Circuit)

system registers

Chapter 7

1.C200.0000 CXTurbo graphics subsystem Chapter 6

1.E000.0000 TURBOchannel interface

registers

Section 3.2

TURBOchannel I/O Registers 3–1

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 343 344

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